Light emitting devices (LEDs), and particularly those operating at greater than approximately a quarter watt, generally include a semiconductor element that provides the light, and one or more non-semiconductor elements that provide mechanical support, electrical connections, thermal dissipation, wavelength conversion, and so on.
As the popularity and the field of use of solid-state LEDs continue to expand, the potential for profit from large quantity sales increases, as does the competition for such sales among manufacturers. In such an environment, the even minor savings in per-unit costs can have a major impact on profitability. Accordingly, manufacturers of LEDs strive to reduce material costs and manufacturing costs.
FIG. 1 illustrates a conventional medium-to-high power LED comprising semiconductor elements 110 and at least two non-semiconductor elements: a ceramic substrate 120, and a pair of electrodes 122. As can be seen, in this embodiment, the ceramic substrate 120 is well over twice the area of the light emitting semiconductor structure 110; the extra area primarily being used to facilitate external connections to the semiconductor structure 110 via the electrodes 122. Accordingly, the substrate 120 accounts for a relatively significant portion of the material cost of the device. Additionally, placing the semiconductor structure 110 on the substrate 120 generally requires a precise pick-and-place process, which adds to the manufacturing cost of the device.
U.S. Pat. No. 7,329,905, “CHIP-SCALE METHODS FOR PACKAGING LIGHT EMITTING DEVICES AND CHIP-SCALE PACKAGED LIGHT EMITTING DEVICES”, issued 12 Feb. 2008 to Ibbetson et al. discloses a technique that uses wafer bonding to eliminate the pick-and-place process, and to reduce the size of the supporting substrate. As illustrated in FIG. 2A, a first wafer includes a substrate 212 upon which multiple LED structures 216 are formed, with contacts 218 at the top of the structures. A second wafer includes a carrier substrate 220 that includes through-hole vias 222, with contacts 228, 238 at the top and bottom of the carrier substrate, respectively. As illustrated in FIG. 2B, the first wafer is inverted and bonded to the second wafer, the contacts 218 of the LED structures being coupled to corresponding contacts 228 at the top of the carrier substrate. Optionally, to reduce interference with the light output from the top of the LED structures, the growth substrate 212 of the first wafer can be thinned or removed. The resultant wafer bonded structure is subsequently diced/singulated (dashed lines) into individual light emitting devices, with contacts 238 at the bottom of the carrier substrate for external connections to the LED structure. These devices can then be placed upon a printed circuit board and coupled to corresponding electrodes on the board, generally using solder reflow techniques.
Although the techniques of U.S. Pat. No. 7,329,905 eliminate the need to pick-and-place individual LED structures, and reduce the substrate area beyond the LED structure, compared to the conventional structure of FIG. 1, further cost reductions, or simplifications, in material and/or manufacturing, would be advantageous.